1. Field of the Invention
The present invention relates to a method and apparatus for transferring data among various components of a computer system. More particularly, the present invention relates to an improved computer bus that is capable of transferring data at an increased rate by using address and control lines to transfer data during part of a bus cycle.
2. Art Background
In a typical computer system, a central processing unit (CPU) reads from, and writes data to, peripheral devices and other components which comprise the data processing system. This communication between devices is frequently accomplished by means of a bus that interconnects all of the components of the computer system. The speed at which the bus transfers data directly limits the overall speed of the computer system. An example of a bus may be found in U.S. patent application Ser. No. 387,599, filed Jun. 28, 1989, titled High Speed Bus with Virtual Memory Data Transfer Capability.
A common constraint on the data transfer rate between components coupled to a bus is the size of the bus itself. Essentially, a bus is a collection of wires connecting the various components of a computer system. In addition to address lines, size lines and data lines, the bus will typically contain clock signal lines, power lines, and other control lines. As a general rule, the speed of the bus can be increased simply by adding more lines to the bus. This allows the bus to carry more data during each clock cycle. For example, a computer system which normally transfers data across 32 lines is able to transfer 4 bytes of data each clock cycle. If 64 data lines are used, the computer system is able to transfer 8 bytes of data each clock cycle. Therefore, increasing the number of available data lines proportionately increases the rate at which a bus may transfer data.
However, simply increasing the number lines in a bus may not lead to a desirable result. Buses that contain a large number of lines are subject to two significant disadvantages when compared to smaller buses. First, they are costly and more difficult to design and build. Second, because of the increased number of connections and interfaces and the greater potential for interference, large buses are generally more likely to malfunction than small buses. Therefore, a balance must be sought between the competing goals of increasing the number of lines in a bus to obtain higher data transfer rates and minimizing the number of lines in a bus to reduce cost and improve reliability.
An additional consideration when designing a bus is the compatibility of different types of peripheral devices which may connect to the bus. A computer system may contain various devices which are capable of operating at different data transfer rates. If a number of different devices are present in the computer system, it is essential that a bus have the flexibility to operate at different rates of transfer so that it is capable of communicating with each device at the fastest possible rate. Furthermore, if some of the devices are limited to only one rate of transfer it is also desirable that a means be provided that can disable a device when it is accessed in a transfer rate which the device does not support.
Two types of buses are currently in use; a multiplexed address bus and non-multiplexed address bus. In a multiplexed address bus, address and data travel over the same wires at different times. In a non-multiplexed address bus, address and data travel over different wires at the same time.